Avago Technologies LSI53C825AE User Manual
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Functional Description
2.4.8.1 Data Paths
The data path through the LSI53C825A is dependent on whether data is
being moved into or out of the chip, and whether SCSI data is being
transferred asynchronously or synchronously.
The following steps determine if any bytes remain in the data path when
the chip halts an operation:
Asynchronous SCSI Send –
Step 1.
If the DMA FIFO size is set to 88 bytes, look at the
and
registers and calculate
if there are bytes left in the DMA FIFO. To make this calculation,
subtract the seven least significant bits of the
register from the 7-bit value of the
register. AND the result with 0x7F for a byte count
between zero and 88.
If the DMA FIFO size is set to 536 bytes (using bit 5 of the
register), subtract the 10 least significant
bits of the
register from the 10-bit
value of the DMA FIFO Byte Offset Counter, which consists of
bits [1:0] in the
register and bits [7:0]
of the DMA FIFO register. AND the result with 0x3FF for a byte
count between zero and 536.
Step 2.
Read bit 5 in the
and
registers to determine if any bytes are left in the
register. If bit 5 is set in the
SSTAT0 or SSTAT2, then the least significant byte or the most
significant byte in the
register
is full, respectively. Checking this bit also reveals bytes left in
the
register from a Chained
Move operation with an odd byte count.
Synchronous SCSI Send –
Step 1.
If the DMA FIFO size is set to 88 bytes, look at the
and
registers and calculate
if there are bytes left in the DMA FIFO. To make this calculation,
subtract the seven least significant bits of the