Avago Technologies LSI53C825AE - Manual (Page 265)

PCI and External Memory Interface Timing Diagrams 6-37
Figure 6.24 Write Cycle, Normal/Fast Memory (
≥
64 Kbytes), Multiple Byte Access (Cont.)
In
16 18 19 22 24 26 28 30 17 33
MAD
(Driven by LSI53C825A)
GPIO2_MAS2/
(Driven by LSI53C825A)
MAS0/
(Driven by LSI53C825A)
MCE/
(Driven by LSI53C825A)
MOE/
(Driven by LSI53C825A)
MWE/
(Driven by LSI53C825A)
CLK
(Driven by System)
PAR
(Driven by Master-Addr;
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C825A)
STOP/
(Driven by LSI53C825A)
DEVSEL/
(Driven by LSI53C825A)
AD
(Driven by Master-Addr;
C_BE/
(Driven by Master)
FRAME/
(Driven by Master)
LSI53C825A-Data)
LSI53C825A-Data)
MAS1/
(Driven by LSI53C825A)
Lower
Address
Byte Enable
Data In
20 21 23 25 27 29 31 32
Data
Out Data Out