Avago Technologies LSI53C825AE - Manual (Page 259)

PCI and External Memory Interface Timing Diagrams 6-31
Figure 6.20 Burst Write (Cont.)
t
1
t
2
Addr
Out
BE
Data
Out
CMD
t
1
t
2
BE
Data
Out
Data
Out
CLK
(Driven by System)
GPIO0_
FETCH/
PAR
(Driven by LSI53C825A)
IRDY/
(Driven by LSI53C825A)
TRDY/
(Driven by Target)
STOP/
(Driven by Target)
DEVSEL/
(Driven by Target)
AD
(Driven by LSI53C825A)
C_BE/
(Driven by LSI53C825A)
GNT/
(Driven by Arbiter)
FRAME/
(Driven by LSI53C825A)
(Driven by LSI53C825A)
REQ/
(Driven by LSI53C825A)
GPIO1_
MASTER/
(Driven by LSI53C825A)