Avago Technologies LSI53C825AE - Manual (Page 89)

LSI53C825A/825AE PCI to SCSI I/O Processor 4-1
Chapter 4
Registers
This chapter describes all LSI53C825A registers and is divided into the
following sections:
•
Section 4.1, “Configuration Registers”
•
Section 4.2, “Operating Registers”
4.1 Configuration Registers
The Configuration registers are accessible only by the system BIOS
during PCI configuration cycles, and they are not available to the user at
any time. These registers can be accessed by SCRIPTS or the host
processor. The lower 128 bytes hold configuration data while the upper
128 bytes hold the LSI53C825A operating registers, which are described
in
Chapter 5, “SCSI SCRIPTS Instruction Set.” Please note that the
information about lower and upper bytes only applies to the LSI53C825A
and not the LSI53C825AE.
Note: The configuration register descriptions provide general
information only, to indicate which PCI configuration
addresses are supported in the LSI53C825A. For detailed
information, refer to the PCI Specification.
Table 4.1 shows the PCI configuration registers implemented by the
LSI53C825A/825AE.
All PCI-compliant devices, such as the LSI53C825A, must support the
Vendor ID , Device ID , Command , and Status registers. Support of other
PCI-compliant registers is optional. In the LSI53C825A, registers that are
not supported are not writable and return all zeros when read. Only those
registers and bits that are currently supported by the LSI53C825A are
described in this chapter. Reserved bits should not be accessed.