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Figure5.3 i/o instruction register, Figure 5.3 – Avago Technologies LSI53C825AE User Manual

Page 201

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I/O Instruction

5-17

Figure 5.3

I/O Instruction Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

DSPS Register

DCMD Register

DBC Register

R

R

R

R

Set/Clear ATN/

Set/Clear ACK/

Set/Clear Target Mode

Set/Clear Carry

Encoded Destination ID 0

Encoded Destination ID 1

Encoded Destination ID 2

Encoded Destination ID 3

Reserved

Reserved

Reserved

Reserved

Select with ATN/

Table Indirect Mode

Relative Address Mode

Opcode Bit 0

Opcode Bit 1

Opcode Bit 2

1 - Instruction Type - I/O

0 - Instruction Type - I/O

Second 32-bit Word of the I/O Instruction

32-bit Jump Address

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