Avago Technologies LSI53C825AE User Manual
Page 135
Operating Registers
4-47
used for asynchronous transfers. It is possible to use this
bit to determine how many bytes reside in the chip when
an error occurs.
FF4
FIFO Flags, Bit 4
4
This is the most significant bit in the SCSI FIFO Flags
field, with the rest of the bits in
. For a complete description of this field, see the
definition for
, bits [7:4].
SPL1
Latched SCSI parity for SD[15:8]
3
This active HIGH bit reflects the SCSI odd parity signal
corresponding to the data latched into the most
significant byte in the
register.
DIFF
Diffsens Mismatch
2
If this bit is reset, the correct cable type has been
connected for the differential operation. If this bit is set, a
SE cable has been connected to the device’s DIFFSENS
pin.
LDSC
Last Disconnect
1
This bit is used in conjunction with the Connected (CON)
bit in
. It allows the user to
detect the case in which a target device disconnects, and
then some SCSI device selects or reselects the
LSI53C825A. If the Connected bit is asserted and the
LDSC bit is asserted, a disconnect is indicated. This bit
is set when the Connected bit in
is off. This bit is cleared when a Block Move
instruction is executed while the Connected bit in
is on.
SDP1
SCSI SDP1 Parity Signal
0
This bit represents the present state of the SCSI SDP1/
parity signal. It is unlatched and may change as it is read.