Avago Technologies LSI53C825AE - Manual (Page 46)

2-22 Functional Description
Status of SCSI Parity
Signal SCSI Status Zero
(SSTAT0)
, Bit 0
This status bit represents the active HIGH current state
of the SCSI SDP0 parity signal.
SCSI SDP1 Signal SCSI Status Two
(SSTAT2)
, Bit 0
This bit represents the active HIGH current state of the
SCSI SDP1 parity signal.
Latched SCSI Parity SCSI Status Two
(SSTAT2)
, Bit 3
and SCSI Status
One (SSTAT1) ,
Bit 3
These bits reflect the SCSI odd parity signal
corresponding to the data latched into the
SCSI Input
Data Latch (SIDL) register.
Master Parity Error
Enable Chip Test Four
(CTEST4)
, Bit 3
Enables parity checking during master data phases.
Master Data Parity Error DMA Status
(DSTAT)
, Bit 6
Set when the LSI53C825A as a master detects that a
target device has signaled a parity error during a data
phase.
Master Data Parity Error
Interrupt Enable DMA Interrupt
Enable (DIEN)
,
Bit 6
By clearing this bit, a Master Data Parity Error will not
cause IRQ/ to be asserted, but the status bit will be set
in the
DMA Status (DSTAT) register.
Table 2.4 SCSI Parity Control
EPC AESP Description
0 0 Does not check for parity errors. Parity is generated when sending
SCSI data. Asserts odd parity when sending SCSI data.
0 1 Does not check for parity errors. Parity is generated when sending
SCSI data. Asserts even parity when sending SCSI data.
1 0 Checks for odd parity on SCSI data received. Parity is generated
when sending SCSI data. Asserts odd parity when sending SCSI
data.
1 1 Checks for odd parity on SCSI data received. Parity is generated
when sending SCSI data. Asserts even parity when sending SCSI
data.
1. Key:
EPC = Enable Parity Checking (bit 3, SCSI Control Zero (SCNTL0) ).
ASEP = Assert SCSI Even Parity (bit 2, SCSI Control One (SCNTL1) ).
2. This table only applies when the Enable Parity Checking bit is set.
Table 2.3 Bits Used for Parity Control and Generation (Cont.)
BIt Name Location Description