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Avago Technologies LSI53C825AE User Manual

Page 200

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5-16

SCSI SCRIPTS Instruction Set

Wait Select Instruction

1. If the LSI53C825A is selected, it fetches the next

instruction from the address pointed to by the

DMA

SCRIPTS Pointer (DSP)

register.

2. If reselected, the LSI53C825A fetches the next

instruction from the address pointed to by the 32-bit
jump address field stored in the

DMA Next Address

(DNAD)

register. Manually set the LSI53C825A to

Initiator mode when it is reselected.

3. If the CPU sets the SIGP bit in the

SCSI Status Zero

(SSTAT0)

register, the LSI53C825A aborts the Wait

Select instruction and fetches the next instruction from
the address pointed to by the 32-bit jump address
field stored in the

DMA Next Address (DNAD)

register.

Set Instruction

When the SACK/ or SATN/ bits are set, the
corresponding bits in the

SCSI Output Control Latch

(SOCL)

register are set. Do not set SACK/ or SATN/

except for testing purposes. When the target bit is set,
the corresponding bit in the

SCSI Control Zero (SCNTL0)

register is also set. When the carry bit is set, the
corresponding bit in the Arithmetic Logic Unit (ALU) is
set.

Note:

None of the signals are set on the SCSI bus in Target
mode.

Clear Instruction

When the SACK/ or SATN/ bits are cleared, the
corresponding bits are cleared in the

SCSI Output

Control Latch (SOCL)

register. Do not set SACK/ or

SATN/ except for testing purposes. When the target bit is
cleared, the corresponding bit in the

SCSI Control Zero

(SCNTL0)

register is cleared. When the carry bit is

cleared, the corresponding bit in the ALU is cleared.

Note:

None of the signals are cleared on the SCSI bus in the
Target mode.

Figure 5.3

illustrates the I/O Instruction register.