Avago Technologies LSI53C825AE - Manual (Page 284)

A-2 Register Summary
Table A.2 lists the LSI53C825A register map by register name.
Power Management Capabilities 0x42 Read Only 4-15
Power Management Control/Status 0x44 Read Write 4-16
RAM Base Address Two (Memory) SCRIPTS RAM 0x18 Read/Write 4-10
Revision ID 0x08 Read Only 4-7
Status 0x06 Read/Write 4-5
Subsystem ID (SSID) 0x2E Read Only 4-11
Subsystem Vendor ID (SSVID) 0x2C Read Only 4-10
Vendor ID 0x00 Read Only 4-3
Table A.1 Configuration Registers (Cont.)
Register Name Address Read/Write Page
Table A.2 LSI53C825A Register Map
Register Name Address Read/Write Page
Adder Sum Output (ADDER) 0x3C–0x3F (0xBC–0xBF) Read Only 4-71
Chip Test Five (CTEST5) 0x22 (0xA2) Read/Write 4-59
Chip Test Four (CTEST4) 0x21 (0xA1) Read/Write 4-57
Chip Test One (CTEST1) 0x19 (0x99) Read Only 4-52
Chip Test Six (CTEST6) 0x23 (0xA3) Read/Write 4-61
Chip Test Three (CTEST3) 0x1B (0x9B) Read/Write 4-54
Chip Test Two (CTEST2) 0x1A (0x9A) Read/Write 4-53
Chip Test Zero (CTEST0) 0x18 (0x98) Read/Write 4-52
Data Structure Address (DSA) 0x10–0x13 (0x90–0x93) Read/Write 4-48
DMA Byte Counter (DBC) 0x24–0x26 (0xA4–0xA6) Read/Write 4-62
DMA Command (DCMD) 0x27 (0xA7) Read/Write 4-63
DMA Control (DCNTL) 0x3B (0xBB) Read/Write 4-69
DMA FIFO (DFIFO) 0x20 (0xA0) Read/Write 4-56