Avago Technologies LSI53C825AE - Manual (Page 260)

6-32 Specifications
6.4.3 External Memory Timing
Figure 6.21 through Figure 6.30 describe LSI53C825A External Memory
timing.
Figure 6.21 Read Cycle, Normal/Fast Memory (
≥
64 Kbytes), Single Byte Access
CLK
MAD
(Addr driven by LSI53C825A;
Data driven by Memory)
MAS2/
(Driven by LSI53C825A)
MAS1/
(Driven by LSI53C825A)
MCE/
(Driven by LSI53C825A)
MOE/
(Driven by LSI53C825A)
MWE/
(Driven by LSI53C825A)
t
11
t
12
t
13
t
15f
t
14f
t
16f
t
18
t
17
t
19
Higher
Address
1. 2. 3.
1. Middle Address 2. Lower Address 3. Valid Read Data
MAS0/
(Driven by LSI53C825A)