Avago Technologies LSI53C825AE - Manual (Page 295)

Index IX-5
jump (Cont.)
call a relative address 5-34
call an absolute address 5-34
if true/false 5-35
instruction 5-29
L
last disconnect (LDSC) 4-47
latched SCSI parity
(SDP0L) 4-45
for SD[15:8] (SPL1) 4-47
latency
timer (LT[7:0]) 4-8
load/store 5-41
lost arbitration (LOA) 4-44
LSI53C700 family compatibility (COM) 4-70
M
MAD bus programming
MAD[3:1] 3-17
manual start mode (MAN) 4-66
master
control for set or reset pulses (MASR) 4-59
data parity error (MDPE) 4-41
,
4-67
enable (ME) 4-80
parity error enable (MPEE) 4-58
max SCSI synchronous offset (MO[4:0]) 4-34
max_lat (ML[7:0]) 4-14
maximum stress ratings 6-2
memory
I/O address/DSA offset 5-42
move instructions 5-36
memory access control (MACNTL) 4-79
min_gnt (MG[7:0]) 4-13
move to/from SFBR cycles 5-27
N
next_item_ptr (NIP[7:0]) 4-15
no flush 5-37
store instruction only 5-41
O
opcode 5-9
,
5-14
,
5-26
,
5-29
operating conditions 6-2
operating registers
general information 4-18
operator 5-26
P
parity
error
(PAR) 4-75
PCI
and external memory interface timing diagrams 6-13
PCI commands 2-2
PCI configuration registers 4-1
base address one (memory) 4-9
base address zero (I/O) 4-9
class code 4-7
command 4-3
device ID 4-3
expansion ROM base address 4-11
header type 4-9
interrupt line 4-13
interrupt pin 4-13
latency timer 4-8
max_lat 4-14
min_gnt 4-13
revision ID 4-7
status 4-5
vendor ID 4-3
PCI configuration space 2-1
PCI I/O space 2-2
PCI memory space 2-2
prefetch
enable (PFEN) 4-68
flush (PFF) 4-68
R
read
modify-write cycles 5-26
write instructions 5-24
write system memory from SCRIPTS 5-38
read/write
instructions 5-24
,
5-27
system memory from SCRIPTS 5-38
register
address 5-41
address - A[6:0] 5-26
register addresses
PCI configuration registers
0x02 4-3
0x04 4-3
0x06 4-5
0x08 4-7
0x09 4-7
0x0D 4-8
0x0E 4-9
0x10 4-9
0x3D 4-13
0x3E 4-13
0x3F 4-14
relative 5-21
relative addressing mode 5-19
,
5-33
reselect
instruction 5-15
reselected (RSL) 4-71
,
4-74
Reserved 4-80
reset
input 6-12
SCSI offset (ROF) 4-88
response ID zero (RESPID0) 4-85
return instruction 5-32
S
scratch
byte register (SBR) 4-68
register A (SCRATCHA) 4-64
register B (SCRATCHB) 4-94
registers C–R (SCRATCHC–SCRATCHR) 4-94
scratcha/b operation (SRTCH) 4-53
SCRIPTS
interrupt instruction received (SIR) 4-41
,
4-67
SCRIPTS processor 2-11
performance 2-11