Avago Technologies LSI53C825AE - Manual (Page 102)

4-14 Registers
Register: 0x3F
Max_Lat
Read Only
ML Max_Lat [7:0]
This register is used to specify the desired settings for
latency timer values. Max_Lat is used to specify how
often the device needs to gain access to the PCI bus.
The value specified in these registers is in units of
0.25 microseconds. The LSI53C825A sets this register to
0x40.
Register: 0x40
Capability ID
Read Only
CID Cap_ID [7:0]
This register indicates the type of data structure currently
being used. It is set to 0x01, indicating the Power
Management Data Structure. Only the LSI53C825AE
sets this register to 0x01.
7 0
ML
0 1 0 0 0 0 0 0
7 0
CID
0 0 0 0 0 0 0 1