Avago Technologies LSI53C825AE - Manual (Page 103)

Configuration Registers 4-15
Register: 0x41
Next Item Pointer
Read Only
NIP Next_Item_Ptr [7:0]
This register describes the location of the next item in the
function’s capability list. The default value for this register
is 0x00, indicating that power management is the last
capability in the linked list of extended capabilities. This
register applies to the LSI53C825AE only.
Register: 0x42
Power Management Capabilities
Read Only
This register applies to the LSI53C825AE only and indicates the power
management capabilities.
PMES[4:0] PME Support [15:11]
This field is always set to 00000b because the
LSI53C825AE does not provide a PME signal.
D2S D2 Support 10
This device does not support the D2 power management
state.
D1S D1 Support 9
This device does not support the D1 power management
state.
7 0
NIP
0 0 0 0 0 0 0 0
15 11 10 9 8 6 5 4 3 2 0
PMES[4:0] D2S D1S R DSI APS PMEC VER[2:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1