Scsi longitudinal parity (slpar) – Avago Technologies LSI53C825AE User Manual
Page 166
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Registers
Register: 0x44 (0xC4)
SCSI Longitudinal Parity (SLPAR)
Read/Write
SLPAR
SCSI Longitudinal Parity
[7:0]
The
SCSI Longitudinal Parity (SLPAR)
register consists
of two multiplexed bytes; other register bit settings
determine what is displayed at this memory location at
any given time. When bit 5 in the
(SLPMD) register is cleared, the chip XORs
the high and low bytes of the
register together to give a single-byte value
which is displayed in the
register. If the SLPMD bit is set, then the
register shows either the
high byte or the low byte of the SLPAR word. The SLPAR
High Byte Enable bit,
, bit 4,
determines which byte of the
register is visible on the
register at any given time. If this bit is
cleared, the
SCSI Longitudinal Parity (SLPAR)
register
contains the low byte of the SLPAR word; if it is set, the
SCSI Longitudinal Parity (SLPAR)
register contains the
high byte of the SLPAR word.
This register performs a bytewise longitudinal parity
check on all SCSI data received or sent through the SCSI
core. If one of the bytes received or sent (usually the last)
is the set of correct even parity bits, SLPAR should go to
zero (assuming it started at zero). As an example,
suppose that the following three data bytes and one
check byte are received from the SCSI bus (all signals
are shown active HIGH):
7
0
SLPAR
x
x
x
x
x
x
x
x