Avago Technologies LSI53C825AE - Manual (Page 94)

4-6 Registers
R Reserved 11
DT[1:0] DEVSEL/ Timing [10:9]
These bits encode the timing of DEVSEL/. These are
encoded as:
These bits are read only and should indicate the slowest
time that a device asserts DEVSEL/ for any bus
command except Configuration Read and Configuration
Write. In the LSI53C825A, 0b01 is supported.
DPR Data Parity Reported 8
This bit is set when the following three conditions are
met:
•
The bus agent asserted PERR/ itself or observed
PERR/ asserted and;
•
The agent setting this bit acted as the bus master for
the operation in which the error occurred and;
•
The Parity Error Response bit in the Command
register is set.
R Reserved [7:5]
NC New Capabilities (NC) 4
This bit is set to indicate a list of extended capabilities
such as PCI Power Management. This bit is Read Only,
and applies to the LSI53C825AE only.
R Reserved [3:0]
0b00 Fast
0b01 Medium
0b10 Slow
0b11 Reserved