Avago Technologies LSI53C825AE - Manual (Page 296)

IX-6 Index
SCSI
ATN condition - target mode (M/A) 4-71
bus control lines (SBCL) 4-39
bus data lines (SBDL) 4-93
C_D/ signal (C_D) 4-45
chip ID (SCID) 4-30
clock (SCLK) 4-87
control enable (SCE) 4-88
control one (SCNTL1) 4-23
control three (SCNTL3) 4-28
control two (SCNTL2) 4-26
control zero (SCNTL0) 4-20
core 2-10
data high impedance (ZSD) 4-57
destination ID (SDID) 4-35
differential mode 2-28
disconnect unexpected (SDU) 4-26
encoded destination ID 5-22
FIFO test read (STR) 4-90
FIFO test write (STW) 4-91
first byte received (SFBR) 4-37
gross error (SGE) 4-71
,
4-74
I_O/ signal (I/O) 4-45
input data latch (SIDL) 4-92
instructions
I/O 5-14
read/write 5-24
interrupt enable one (SIEN1) 4-72
interrupt enable zero (SIEN0) 4-70
interrupt pending (SIP) 4-50
interrupt status one (SIST1) 4-76
interrupt status zero (SIST0) 4-73
isolation mode (SISO) 4-87
longitudinal parity (SLPAR) 4-77
loopback mode (SLB) 4-88
low level mode (LOW) 4-89
MSG/ signal (MSG) 4-45
output control latch (SOCL) 4-38
output data latch (SODL) 4-93
parity error (PAR) 4-72
phase 5-12
,
5-33
phase mismatch - initiator mode 4-71
reset condition (RST) 4-72
RST/ received (RST) 4-75
RST/ signal (RST) 4-44
SDP0/ parity signal (SDP0) 4-44
SDP1/ parity signal (SDP1) 4-47
selected as ID (SSAID[3:0]) 4-86
selector ID (SSID) 4-39
signals 3-10
status one (SSTAT1) 4-44
status two (SSTAT2) 4-46
status zero (SSTAT0) 4-43
synchronous offset maximum (SOM) 4-87
synchronous offset zero (SOZ) 4-86
synchronous transfer period (TP[2:0]) 4-31
termination 2-29
test one (STEST1) 4-87
test three (STEST3) 4-90
test two (STEST2) 4-88
test zero (STEST0) 4-86
timer one (STIME1) 4-83
timer zero (STIME0) 4-81
TolerANT technology 1-3
transfer (SXFER) 4-31
true end of process 4-54
valid (VAL) 4-39
wide residue (SWIDE) 4-78
SCSI bus interface 2-27
to
2-33
SCSI core 2-10
SCSI instructions
block move 5-6
SCSI SCRIPTS operation 5-2
sample instruction 5-3
SCSI-1 transfers (differential 4.17 Mbytes) 6-49
SCSI-1 transfers (single-ended 5.0 Mbytes) 6-49
SCSI-2 fast transfers 10.0 Mbytes (8-bit transfers) or 20.0
Mbytes (16-bit transfers) 40 MHz clock 6-50
SCSI-2 fast transfers 10.0 Mbytes (8-bit transfers) or 20.0
Mbytes (16-bit transfers) 50 MHz clock 6-50
second dword 5-13
,
5-23
,
5-26
,
5-36
,
5-38
,
5-42
select
instruction 5-18
with ATN/ 5-22
with SATN/ on a start sequence (WATN) 4-22
selected (SEL) 4-71
,
4-74
selection or reselection time-out (STO) 4-73
,
4-76
selection response logic test (SLT) 4-86
semaphore (SEM) 4-49
set instruction 5-16
,
5-19
set/clear
carry 5-22
SACK/ 5-23
shadow register test mode (SRTM) 4-58
SIDL
least significant byte full (ILF) 4-43
most significant byte full (ILF1) 4-46
signal process (SIGP) 4-49
,
4-53
signals
address and data signals 3-7
arbitration signals 3-9
error reporting signals 3-9
interface control signals 3-8
SCSI signals 3-10
simple arbitration 4-20
single
step interrupt (SSI) 4-41
,
4-67
step mode (SSM) 4-69
single-ended operation 2-27
SLPAR high byte enable (SLPHBEN) 4-27
SLPAR mode (SLPMD) 4-27
SODL
least significant byte full (OLF) 4-43
most significant byte full (OLF1) 4-46
SODR
least significant byte full (ORF) 4-43
most significant byte full (ORF1) 4-46
software reset (SRST) 4-49
source
I/O-memory enable (SIOM) 4-65
stacked interrupts 2-39
start
address 5-13
,
5-23
DMA operation (STD) 4-69
SCSI transfer (SST) 4-25
sequence (START) 4-21
Storage Device Management System (SDMS) 2-12
stress ratings 6-2
subsystem ID
(SID[15:0]) 4-11
subsystem vendor ID
(SVID[15:0]) 4-10