4 pci cache mode, 1 load and store instructions, 2 3.3 v/5 v pci interface – Avago Technologies LSI53C825AE User Manual
Page 41: 3 additional access to general purpose pins, Section 2.4, “pci cache mode
PCI Cache Mode
2-17
2.4 PCI Cache Mode
The LSI53C825A supports the PCI specification for an 8-bit
register located in PCI configuration space. The
register provides the ability to sense and react to nonaligned addresses
corresponding to cache line boundaries. In conjunction with the
register, the PCI commands Read Line, Read Multiple, and
Write and Invalidate are each software enabled or disabled to allow the
user full flexibility in using these commands. For more information on PCI
cache mode operations, refer to
Chapter 3, “Signal Descriptions.”
2.4.1 Load and Store Instructions
The LSI53C825A supports the Load and Store instruction type, which
simplifies the movement of data between memory and the internal chip
registers. It also enables the LSI53C825A to transfer bytes to addresses
relative to the
register. For more
information on the Load and Store instructions, refer to
2.4.2 3.3 V/5 V PCI Interface
The LSI53C825A can attach directly to a 3.3 V or a 5 V PCI interface,
due to separate V
DD
pins for the PCI bus drivers. This allows the devices
to be used on the universal board recommended by the PCI Special
Interest Group.
2.4.3 Additional Access to General Purpose Pins
The LSI53C825A can access the GPIO0 and GPIO1 general purpose
pins through register bits in the PCI configuration space, instead of using
the
General Purpose Pin Control (GPCNTL)
register in the operating
register space to control these pins. In the LSI Logic SDMS software, the
configuration bits control pins as the clock and data lines, respectively.
To access the GPIO[1:0] pins through the configuration space, connect
a 4.7 k
Ω
resistor between the MAD7 pin and V
SS
. MAD7 contains an
internal pull-up that is sensed shortly after chip reset. If the pin is sensed
high, GPIO[1:0] access is disabled; if it is low, GPIO[1:0] access is
enabled. Additionally, if GPIO[1:0] access has been enabled through the