Avago Technologies LSI53C825AE - Manual (Page 11)

Contents xi
6.6 External Clock 6-11
6.7 Reset Input 6-12
6.8 Interrupt Output 6-13
6.9 PCI Configuration Register Read 6-15
6.10 PCI Configuration Register Write 6-16
6.11 Operating Register/SCRIPTS RAM Read 6-17
6.12 Operating Register/SCRIPTS RAM Write 6-18
6.13 External Memory Read 6-20
6.14 External Memory Write 6-22
6.15 Nonburst Opcode Fetch 6-24
6.16 Burst Opcode Fetch 6-25
6.17 Back-to-Back Read 6-26
6.18 Back-to-Back Write 6-27
6.19 Burst Read 6-28
6.20 Burst Write 6-30
6.21 Read Cycle, Normal/Fast Memory (
≥
64 Kbytes),
Single Byte Access 6-32
6.22 Write Cycle, Normal/Fast Memory (
≥
64 Kbytes),
Single Byte Access 6-33
6.23 Read Cycle, Normal/Fast Memory (
≥
64 Kbytes),
Multiple Byte Access 6-34
6.24 Write Cycle, Normal/Fast Memory (
≥
64 Kbytes),
Multiple Byte Access 6-36
6.25 Read Cycle, Slow Memory (
≥
64 Kbytes) 6-38
6.26 Write Cycle, Slow Memory (
≥
64 Kbytes) 6-39
6.27 Read Cycle, Normal/Fast Memory (
≥
64 Kbytes) 6-40
6.28 Write Cycle, Normal/Fast Memory (
≥
64 Kbytes) 6-41
6.29 Read Cycle, Slow Memory (
≤
64 Kbytes) 6-42
6.30 Write Cycle, Slow Memory (
≤
64 Kbytes) 6-43
6.31 Initiator Asynchronous Send 6-45
6.32 Initiator Asynchronous Receive 6-46
6.33 Target Asynchronous Send 6-47
6.34 Target Asynchronous Receive 6-48
6.35 Initiator and Target Synchronous Transfers 6-48
6.36 LSI53C825A 160 Pin PQFP (PF) Mechanical Drawing 6-52
B.1 64 Kbyte Interface with 200 ns Memory B-1