Avago Technologies LSI53C825AE - Manual (Page 106)

4-18 Registers
4.2 Operating Registers
This section contains descriptions of all LSI53C825A operating registers.
Table 4.2 , the register map, lists registers by operating and configuration
addresses. The terms “set” and “assert” are used to refer to bits that are
programmed to a binary one. Similarly, the terms “deassert,” “clear,” and
“reset” are used to refer to bits that are programmed to a binary zero.
Any bits marked as reserved should always be written to zero; mask all
information read from them. Reserved bit functions may be changed at
any time. Unless otherwise indicated, all bits in registers are active high,
that is, the feature is enabled by setting the bit. The bottom row of every
register diagram shows the default register values, which are enabled
after the chip is powered on or reset.
Note: The only register that the host CPU can access while the
LSI53C825A is executing SCRIPTS is the
Interrupt Status
(ISTAT) register; attempts to access other registers will
interfere with the operation of the chip. However, all
operating registers are accessible with SCRIPTS. All read
data is synchronized and stable when presented to the PCI
bus.
The LSI53C825A cannot fetch SCRIPTS instructions from
the operating register space. Instructions must be fetched
from system memory or the internal SCRIPTS RAM.