Avago Technologies LSI53C825AE - Manual (Page 12)

xii Contents
B.2 64 Kbyte Interface with 150 ns Memory B-2
B.3 256 Kbyte Interface with 150 ns Memory B-3
B.4 512 Kbyte Interface with 150 ns Memory B-4
Tables
2.1 PCI Bus Commands and Encoding Types 2-3
2.2 External Memory Support 2-16
2.3 Bits Used for Parity Control and Generation 2-21
2.4 SCSI Parity Control 2-22
2.5 SCSI Parity Errors and Interrupts 2-23
2.6 Differential Mode 2-28
3.1 LSI53C825A, LSI53C825AJ, LSI53C825AE, and
LSI53C825AJE Power and Ground Pins
3-4
3.2 System Signals 3-6
3.3 Address and Data Signals 3-7
3.4 Interface Control Signals 3-8
3.5 Arbitration Signals 3-9
3.6 Error Reporting Signals 3-9
3.7 SCSI Bus Interface Signals 3-10
3.8 Additional Interface Signals 3-11
3.9 External Memory Interface Signals 3-14
3.10 JTAG Signals (LSI53C825AJ, LSI53C825AJE Only) 3-15
3.11 Subsystem Data Configuration Table for the
LSI53C825AE (PCI Rev ID 0x26)
3-16
3.12 Subsystem Data Configuration Table for the
LSI53C825A (PCI Rev ID 0x14) Revision G Only
3-16
3.13 External Memory Support 3-17
4.1 PCI Configuration Register Map 4-2
4.2 LSI53C825A Register Map 4-19
4.3 Synchronous Clock Conversion Factor 4-29
4.4 Examples of Synchronous Transfer Periods and
Rates for SCSI-1
4-33
4.5 Example Transfer Periods and Rates for Fast SCSI-2 4-33
4.6 Maximum Synchronous Offset 4-34
4.7 Timeout Periods 4-82
4.8 Timeout Periods, 50 MHz Clock 4-83
5.1 SCRIPTS Instructions 5-3
5.2 Read/Write Instructions 5-27