Avago Technologies LSI53C825AE - Manual (Page 133)

Operating Registers 4-45
SDP0L Latched SCSI Parity 3
This bit reflects the SCSI parity signal (SDP0/),
corresponding to the data latched in the
SCSI Input Data
Latch (SIDL) . It changes when a new byte is latched into
the least significant byte of the SCSI Input Data Latch
(SIDL) register. This bit is active high, in other words, it
is set when the parity signal is active.
MSG SCSI MSG/ Signal 2
C/D SCSI C_D/ Signal 1
I/O SCSI I_O/ Signal 0
These SCSI phase status bits are latched on the
asserting edge of SREQ/ when operating in either the
FF4
(SSTAT2 bit 4) FF3 FF2 FF1 FF0
Bytes or
Words in
the SCSI
FIFO
0 0 0 0 0 0
0 0 0 0 1 1
0 0 0 1 0 2
0 0 0 1 1 3
0 0 1 0 0 4
0 0 1 0 1 5
0 0 1 1 0 6
0 0 1 1 1 7
0 1 0 0 0 8
0 1 0 0 1 9
0 1 0 1 0 10
0 1 0 1 1 11
0 1 1 0 0 12
0 1 1 0 1 13
0 1 1 1 0 14
0 1 1 1 1 15
1 0 0 0 0 16