Avago Technologies LSI53C825AE User Manual
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Registers
Disable Single Initiator Response
4
If this bit is set, the LSI53C825A ignores all bus-initiated
selection attempts that employ the single-initiator option
from SCSI-1. In order to select the LSI53C825A while this
bit is set, the LSI53C825A SCSI ID and the initiator’s
SCSI ID must both be asserted. Assert this bit in
SCSI-2 systems so that a single bit error on the SCSI bus
is not interpreted as a single initiator response.
S16
16-Bit System
3
If this bit is set, all devices in the SCSI system
implementation are assumed to be 16-bit. This causes
the LSI53C825A to always check the parity bit for SCSI
IDs 15–8 during bus-initiated selection or reselection,
assuming parity checking has been enabled. If an 8-bit
SCSI device attempts to select the LSI53C825A while
this bit is set, the LSI53C825A ignores the selection
attempt. This is because the parity bit for IDs 15–8 are
not driven. See the description of the Enable Parity
Checking bit in the
register
for more information.
TTM
Timer Test Mode
2
Asserting this bit facilitates testing of the selection
time-out, general purpose, and handshake-to-handshake
timers by greatly reducing all three time-out periods.
Setting this bit starts all three timers and if the respective
bits in the
SCSI Interrupt Enable One (SIEN1)
register
are asserted, the LSI53C825A generates interrupts at
time-out. This bit is intended for internal manufacturing
diagnosis and should not be used.
CSF
Clear SCSI FIFO
1
Setting this bit causes the “full flags” for the SCSI FIFO
to be cleared. This empties the FIFO. This bit is
self-clearing. In addition to the SCSI FIFO pointers, the
SIDL, SODL, and SODR full bits in the
and
are cleared.
STW
SCSI FIFO Test Write
0
Setting this bit places the SCSI core into a test mode in
which the FIFO is easily read or written. While this bit is
set, writes to the least significant byte of the