Avago Technologies LSI53C825AE - Manual (Page 267)

PCI and External Memory Interface Timing Diagrams 6-39
Figure 6.26 Write Cycle, Slow Memory (
≥
64 Kbytes)
CLK
MAD
(Driven by LSI53C825A)
MAS2/
(Driven by LSI53C825A)
MAS0/
(Driven by LSI53C825A)
MCE/
(Driven by LSI53C825A)
MOE/
(Driven by LSI53C825A)
MWE/
(Driven by LSI53C825A)
Higher
Address
t
11
t
12
t
13
t
24s
t
25
t
20
t
23
t
22s
t
26
t
21
1. 2.
1. Middle Address 2. Lower Address
Valid Write Data
MAS1/
(Driven by LSI53C825A)