Avago Technologies LSI53C825AE - Manual (Page 105)

Configuration Registers 4-17
PEN PME Enable 8
The LSI53C825A always returns a zero for this bit to
indicate that PME assertion is disabled.
R Reserved [7:2]
PWS Power State [1:0]
Bits [1:0] are used to determine the current power state
for the LSI53C825A. They are used to place the
LSI53C825A in a new power state. Power states are
defined as:
Register: 0x46
Bridge Support Extensions (PMCSR_BSE)
Read Only
BSE[7:0] Bridge Support Extensions [7:0]
This register applies to the LSI53C825A only and can
support PCI bridge specific functionality, if required. The
default value always returns 0x00.
Register: 0x47
Data
Read Only
DATA[7:0] Data [7:0]
This register applies to the LSI53C825AE only and
provides an optional mechanism for the function to report
state dependent operating data. The LSI53C825AE
returns 0x00 as the default value.
0b00 D0
0b01 Reserved
0b10 Reserved
0b11 D3 hot
7 0
BSE
0 0 0 0 0 0 0 0
7 0
DATA
0 0 0 0 0 0 0 0