Avago Technologies LSI53C825AE - Manual (Page 142)

4-54 Registers
bit is clear, the Scratch Register A (SCRATCHA) and
Scratch Register B (SCRATCHB) registers return to
normal operation.
Note: Bit 3 is the only writable bit in this register. All other bits are
read only. When modifying this register, all other bits must
be written to zero. Do not execute a Read-Modify-Write to
this register.
TEOP SCSI True End of Process 2
This bit indicates the status of the LSI53C825A internal
TEOP signal. The TEOP signal acknowledges the
completion of a transfer through the SCSI portion of the
LSI53C825A. When this bit is set, TEOP is active. When
this bit is cleared, TEOP is inactive.
DREQ Data Request Status 1
This bit indicates the status of the LSI53C825A internal
Data Request signal (DREQ). When this bit is set, DREQ
is active. When this bit is cleared, DREQ is inactive.
DACK Data Acknowledge Status 0
This bit indicates the status of the LSI53C825A internal
Data Acknowledge signal (DACK/). When this bit is set,
DACK/ is inactive. When this bit is cleared, DACK/ is
active.
Register: 0x1B (0x9B)
Chip Test Three (CTEST3)
Read/Write
V[3:0] Chip Revision Level [7:4]
These bits identify the chip revision level for software
purposes. It should have the same value as the lower
nibble of the PCI
Revision ID register, at address 0x08 in
the configuration space.
FLF Flush DMA FIFO 3
When this bit is set, data residing in the DMA FIFO is
transferred to memory, starting at the address in the
DMA
7 4 3 2 1 0
V[3:0] FLF CLF FM WRIE
x x x x 0 0 0 0