Avago Technologies LSI53C825AE - Manual (Page 147)

Operating Registers 4-59
FBL[2:0] FIFO Byte Control [2:0]
These bits steer the contents of the Chip Test Six
(CTEST6) register to the appropriate byte lane of the
64-bit DMA FIFO. If the FBL3 bit is set, then FBL2
through FBL0 determine which of eight byte lanes can be
read or written. When cleared, the byte lane read or
written is determined by the current contents of the
DMA
Next Address (DNAD) and DMA Byte Counter (DBC)
registers. Each of the eight bytes that make up the 64-bit
DMA FIFO is accessed by writing these bits to the proper
value. For normal operation, FBL3 must equal zero.
Register: 0x22 (0xA2)
Chip Test Five (CTEST5)
Read/Write
ADCK Clock Address Incrementor 7
Setting this bit increments the address pointer contained
in the
DMA Next Address (DNAD) register. The DMA
Next Address (DNAD) register is incremented based on
the DNAD contents and the current DMA Byte Counter
(DBC) value. This bit automatically clears itself after
incrementing the DMA Next Address (DNAD) register.
BBCK Clock Byte Counter 6
Setting this bit decrements the byte count contained in
the 24-bit
DMA Byte Counter (DBC) register. It is
decremented based on the DBC contents and the current
DMA Next Address (DNAD) value. This bit automatically
FBL3 FBL2 FBL1 FBL0
DMA FIFO
Byte Lane Pins
0 x x x Disabled N/A
1 0 0 0 0 D[7:0]
1 0 0 1 1 D[15:8]
1 0 1 0 2 D[23:16]
1 0 1 1 3 D[31:24]
7 6 5 4 3 2 1 0
ADCK BBCK DFS MASR DDIR BL2 BO[9:8]
0 0 0 0 0 x x x