Avago Technologies LSI53C825AE User Manual
Page 50
2-26
Functional Description
bits [1:0] in the
register and bits [7:0]
of the DMA FIFO register. AND the result with 0x3FF for a byte
count between zero and 536.
Step 2.
Read bit 7 in the
and
register to determine if any bytes are left in the
register. If bit 7 is set in the
or
, then the
least significant byte or the most significant byte is full,
respectively.
Step 3.
If any wide transfers have been performed using the Chained
Move instruction, read the Wide SCSI Receive bit (
, bit 0) to determine whether a byte is left
in the
register.
Synchronous SCSI Receive –
Step 1.
If the DMA FIFO size is set to 88 bytes, subtract the seven least
significant bits of the
register from
the 7-bit value of the
register. AND the
result with 0x7F for a byte count between zero and 88.
If the DMA FIFO size is set to 536 bytes (using bit 5 of the
register), subtract the 10 least significant
bits of the
register from the 10-bit
value of the DMA FIFO Byte Offset Counter, which consists of
bits [1:0] in the
register and bits [7:0]
of the
register. AND the result with 0x3FF
for a byte count between zero and 536.
Step 2.
Read bits [7:4] of the
register and
bit 4 of the
register, the binary
representation of the number of valid bytes in the SCSI FIFO,
to determine if any bytes are left in the SCSI FIFO.
Step 3.
If any wide transfers have been performed using the Chained
Move instruction, read the Wide SCSI Receive bit (
, bit 0) to determine whether a byte is left
in the
register.
shows how data is moved to/from the SCSI bus in
each of the different modes.