GW Instek APS-1102A User Manual - Manual (Page 237)

6 REMOTE INTERFACE
APS-1102A 6-53
Table6-15. Standard Event Status Register Definitions
Bit Weight Description
PON (7) 128
Power on bit
1 is set to this bit when the power is turned on.
When this register is read, this bit is cleared to 0, and it remains 0 until the power is
turned on again.
URQ (6) 64
User request bit
Always 0 (not used)
CME (5) 32
Command error
1 is set to this bit when a syntax error occurs in the program code.
EXE (4) 16
Execution error
1 is set to this bit when a parameter is out of the setting range or when settings
conflict.
DDE (3) 8
Device definition error
Always 0 (not used)
QYE (2) 4
Query error
1 is set to this bit when there is no data in the buffer containing response messages
when trying to read that buffer, or when the data in the buffer containing response
messages has been lost.
RQC (1) 2
Request control
Always 0 (not used)
1 is set to this bit when all processing of operation complete (OPC) commands has
been completed.

In this device, this bit is always 0.
OPC (0) 1
Operation complete
1 is set to this bit when all processing of operation complete (OPC) commands has
been completed.