Altera Video and Image Processing Suite User Manual
Page 94
Signal
Direction
Description
status_update_int
Output
control
slave port Avalon-MM interrupt signal. When
asserted, the status registers of the IP core have been
updated and the master must read them to determine
what has occurred.
Note: Present only if you turn on Use control port.
vid_clk
Input
Clocked video clock. All the video output signals are
synchronous to this clock.
vid_data
Output
Clocked video data bus. This bus transfers video data into
the IP core.
vid_datavalid
Output
Clocked video data valid signal. Assert this signal when a
valid sample of video data is present on
vid_data
.
vid_f
Output
Clocked video field signal. For interlaced input, this signal
distinguishes between field 0 and field 1. For progressive
video, this signal is unused.
Note: For separate synchronization mode only.
vid_h
Output
Clocked video horizontal blanking signal. This signal is
asserted during the horizontal blanking period of the
video stream.
Note: For separate synchronization mode only.
vid_h_sync
Output
Clocked video horizontal synchronization signal. This
signal is asserted during the horizontal synchronization
period of the video stream.
Note: For separate synchronization mode only.
vid_ln
Output
Clocked video line number signal. Used with the SDI IP
core to indicate the current line number when the
vid_
trs
signal is asserted.
Note: For embedded synchronization mode only.
vid_mode_change
Output
Clocked video mode change signal. This signal is asserted
on the cycle before a mode change occurs.
vid_sof
Output
Start of frame signal. A rising edge (0 to 1) indicates the
start of the video frame as configured by the SOF registers.
vid_sof_locked
Output
Start of frame locked signal. When asserted, the
vid_sof
signal is valid and can be used.
vid_std
Output
Video standard bus. Can be connected to the
tx_std
signal of the SDI IP core (or any other interface) to read
from the
Standard
register.
UG-VIPSUITE
2015.05.04
Clocked Video Interface Signals
4-35
Clocked Video Interface IP Cores
Altera Corporation