Altera Video and Image Processing Suite - Manual (Page 178)

Signal Direction Description
ma_control_av_write
Input
ma_control
slave port Avalon-MM
write
signal. When
you assert this signal, the
ma_control
port accepts new
data from the
writedata
bus.
ma_control_av_writedata
Input
ma_control
slave port Avalon-MM
writedata
bus. The
IP core uses these input lines for write transfers.
read_master_N_av_address
Output
read_master_N
port Avalon-MM
address
bus. This bus
specifies a byte address in the Avalon-MM address space.
read_master_N_av_burstcount
Output
read_master_N
port Avalon-MM
burstcount
signal.
This signal specifies the number of transfers in each burst.
read_master_N_av_clock
Input
read_master_N
port
clock
signal. The interface operates
on the rising edge of the
clock
signal.
read_master_N_av_read
Output
read_master_N
port Avalon-MM
read
signal. The IP core
asserts this signal to indicate read requests from the
master to the system interconnect fabric.
read_master_N_av_readdata
Input
read_master_N
port Avalon-MM
readdata
bus. These
input lines carry data for read transfers.
read_master_N_av_readdata-
valid
Input
read_master_N
port Avalon-MM
readdatavalid
signal.
The system interconnect fabric asserts this signal when the
requested read data has arrived.
read_master_N_av_reset
Input
read_master_N
port reset signal. The interface asynchro‐
nously resets when this signal is high. You must deassert
this signal synchronously to the rising edge of the clock
signal.
read_master_N_av_
waitrequest
Input
read_master_N
port Avalon-MM
waitrequest
signal.
The system interconnect fabric asserts this signal to cause
the master port to wait.
write_master_av_address
Output
write_master
port Avalon-MM
address
bus. This bus
specifies a byte address in the Avalon-MM address space.
write_master_av_burstcount
Output
write_master
port Avalon-MM
burstcount
signal. This
signal specifies the number of transfers in each burst.
write_master_av_clock
Input
write_master
port
clock
signal. The interface operates on
the rising edge of the
clock
signal.
write_master_av_reset
Input
write_master
port
reset
signal. The interface asynchro‐
nously resets when this signal is high. You must deassert
this signal synchronously to the rising edge of the
clock
signal.
write_master_av_waitrequest
Input
write_master
port Avalon-MM
waitrequest
signal. The
system interconnect fabric asserts this signal to cause the
master port to wait.
UG-VIPSUITE
2015.05.04
Deinterlacing Signals 12-19
Deinterlacing IP Cores Altera Corporation
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