Altera Video and Image Processing Suite - Manual (Page 250)

Signal Direction Description
dout_data
Output
dout
port Avalon-ST
data
bus. This bus enables the
transfer of pixel data out of the IP core.
dout_endofpacket
Output
dout
port Avalon-ST
endofpacket
signal. This signal
marks the end of an Avalon-ST packet.
dout_ready
Input
dout
port Avalon-ST
ready
signal. The downstream
device asserts this signal when it is able to receive data.
dout_startofpacket
Output
dout
port Avalon-ST
startofpacket
signal. This signal
marks the start of an Avalon-ST packet.
dout_valid
Output
dout
port Avalon-ST
valid
signal. The IP core asserts this
signal when it produces data.
Test Pattern Generator Control Registers
The width of each register in the Test Pattern Generator control register map is 16 bits. The control data is
read once at the start of each frame and is buffered inside the IP cores, so that the registers can be safely
updated during the processing of a frame or pair of interlaced fields.
After reading the control data, the Test Pattern Generator IP cores produce a control packet that describes
the following image data packet. When the output is interlaced, the control data is processed only before
the first field of a frame, although a control packet is sent before each field.
Table 19-6: Test Pattern Generator Control Register Map
The table below describes the control register map for Test Pattern Generator IP core.
Address Register Description
0
Control
Bit 0 of this register is the
Go
bit, all other bits are unused.
Setting this bit to 0 causes the IP core to stop before control
information is read.
1
Status
Bit 0 of this register is the
Status
bit, all other bits are unused.
The IP core sets this address to 0 between frames. The IP core
sets this address to 1 while it is producing data and cannot be
stopped.
2
Output Width
The width of the output frames or fields in pixels.
Note: Value from 32 up to the maximum specified in the
parameter editor.
3
Output Height
The progressive height of the output frames or fields in pixels.
Note: Value from 32 up to the maximum specified in the
parameter editor.
19-8 Test Pattern Generator Control Registers
UG-VIPSUITE
2015.05.04
Altera Corporation Test Pattern Generator IP Cores
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