Altera Video and Image Processing Suite - Manual (Page 150)

Signal Direction Description
control_byteenable
Output
control
slave port Avalon-MM
byteenable
bus. This bus
enables specific byte lane or lanes during transfers.
Each bit in
byteenable
corresponds to a byte in
writedata
and
readdata
.
• During writes,
byteenable
specifies which bytes are
being written to; the slave ignores other bytes.
• During reads,
byteenable
indicates which bytes the
master is reading. Slaves that simply return
readdata
with no side effects are free to ignore
byteenable
during reads.
Color Space Conversion Control Registers
The width of each register in the Color Space Conversion control register map is 32 bits. To convert from
fractional values, simply move the binary point right by the number of fractional bits specified in the user
interface.
The control data is read once at the start of each frame and is buffered inside the IP cores, so the registers
can be safely updated during the processing of a frame.
Table 10-4: Color Space Converter (CSC) Control Register
The table below describes the control register map for Color Space Converter IP core.
Address Register Description
0
Control
Bit 0 of this register is the
Go
bit, all other bits are unused.
Setting this bit to 0 causes the IP core to stop the next time
control information is read.
1
Status
Bit 0 of this register is the
Status
bit, all other bits are unused.
10-10 Color Space Conversion Control Registers
UG-VIPSUITE
2015.05.04
Altera Corporation Color Space Conversion IP Cores
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