Altera Video and Image Processing Suite - Manual (Page 249)

Signal Direction Description
dout_startofpacket
Output
dout
port Avalon-ST
startofpacket
signal. This signal
marks the start of an Avalon-ST packet.
dout_valid
Output
dout
port Avalon-ST
valid
signal. The IP core asserts this
signal when it produces data.
Table 19-5: Test Pattern Generator II Signals
Signal Direction Description
reset
Input The IP core asynchronously resets when you assert this
signal. You must deassert this signal synchronously to the
rising edge of the clock signal.
clock
Input The main system clock. The IP core operates on the rising
edge of this signal.
control_address
Input
control
slave port Avalon-MM
address
bus. This bus
specifies a word offset into the slave address space.
control_write
Input
control
slave port Avalon-MM
write
signal. When you
assert this signal, the
control
port accepts new data from
the
writedata
bus.
control_writedata
Input
control
slave port Avalon-MM
writedata
bus. The IP
core uses these input lines for write transfers.
control_read
Output
control
slave port Avalon-MM
read
signal. When you
assert this signal, the control port produces new data at
readdata
.
control_readdata
Output
control
slave port Avalon-MM
readdatavalid
bus. The
IP core uses these output lines for read transfers.
control_readdatavalid
Output
control
slave port Avalon-MM
readdata
bus. The IP
core asserts this signal when the
readdata
bus contains
valid data in response to the read signal.
control_waitrequest
Output
control
slave port Avalon-MM
waitrequest
signal.
control_byteenable
Output
control
slave port Avalon-MM
byteenable
bus. This bus
enables specific byte lane or lanes during transfers.
Each bit in
byteenable
corresponds to a byte in
writedata
and
readdata
.
• During writes,
byteenable
specifies which bytes are
being written to; the slave ignores other bytes.
• During reads,
byteenable
indicates which bytes the
master is reading. Slaves that simply return
readdata
with no side effects are free to ignore
byteenable
during reads.
UG-VIPSUITE
2015.05.04
Test Pattern Generator Signals 19-7
Test Pattern Generator IP Cores Altera Corporation
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