Altera Video and Image Processing Suite User Manual
Page 76
Modules
Description
Resolution_detection
• This module uses the
h_sync
,
v_sync
,
de
, and
f
signals to detect the
resolution of the incoming video.
• The resolution consists of:
• width of the line
• width of the active picture region of the line (in samples)
• height of the frame (or fields in the case of interlaced video)
• height of the active picture region of the frame or fields (in lines)
The resolutions are then written into a RAM in the control module.
• The resolution detection module also produces some additional
information.
• It detects whether the video is interlaced by looking at the
f
signal.
It detects whether the video is stable by comparing the length of the
lines. If two outputs of the last three lines have the same length.
then the video is considered stable.
• Finally, it determines if the resolution of the video is valid by
checking that the width and height of the various regions of the
frame has not changed.
Write_buffer_fifo
• This module writes the active picture data, marked by the
de
signal,
into a FIFO that is used to cross over into the
is_clk
clock domain.
• If you set the Color plane transmission format parameter to
Parallel for the output, then the write_buffer_fifo will also convert
any incoming sequential video, marked by the
hd_sdn
signal, into
parallel video before writing it into the FIFO.
• The
Go
bit of the
Control
register must be 1 on the falling edge of
the
v_sync
signal before the write_buffer_fifo module starts writing
data into the FIFO.
• If an overflow occurs due to insufficient room in the FIFO, then the
module stops writing active picture data into the FIFO.
• It waits for the start of the next frame before attempting to write in
video data again.
Control
• This module provides the register file that is used to control the IP
core through an Avalon-MM slave interface.
• It also holds the RAM that contains the detected resolution of the
incoming video and the extracted auxiliary packet which is read by
the av_st_output module, to form the control packets, and can also
be read from the Avalon-MM slave interface.
• The RAM provides the clock crossing between the
vid_clk
and
is_
clk
clock domains.
UG-VIPSUITE
2015.05.04
Modules for Clocked Video Input II IP Core
4-17
Clocked Video Interface IP Cores
Altera Corporation