Altera Video and Image Processing Suite - Manual (Page 56)

Note: The clock and reset signal types are optional. The Avalon-MM master interfaces can operate on a
different clock from the IP core and its other interfaces by selecting the relevant option in the
parameter editor when and if it is available.
A master interface that only performs write transactions do not require the read-only signals. A master
interface that only performs read transactions do not require the write-only signals. To simplify the
Avalon-MM master interfaces and improve efficiency, read-only ports are not present in write-only
masters, and write-only ports are not present in read-only masters. Read-write ports are present in all
Avalon-MM master interfaces.
The external memory access interfaces of the Video and Image Processing Suite IP cores have pipeline
with variable latency feature.
Related Information
Avalon Interface Specifications
Provides more information about these interface types.
Buffering of Non-Image Data Packets in Memory
The Frame Buffer and the Deinterlacing IP cores (when buffering is enabled) route the video stream
through an external memory. Non-image data packets must be buffered and delayed along with the frame
or field they relate to and extra memory space has to be allocated. You must specify the maximum
number of packets per field and the maximum size of each packet to cover this requirement.
The maximum size of a packet is given as a number of symbols, header included. For instance, the size of
an Avalon-ST Video control packet is 10. This size does not depend on the number of channels
transmitted in parallel. Packets larger than this maximum limit may be truncated as extra data is
discarded.
The maximum number of packets is the number of packets that can be stored with each field or frame.
Older packets are discarded first in case of overflow. When frame dropping is enabled, the packets
associated with a field that has been dropped are automatically transferred to the next field and count
towards this limit.
The Frame Buffer and the Deinterlacing IP cores handle Avalon-ST Video control packets differently. The
Frame Buffer processes and discards incoming control packets whereas the Deinterlacing IP cores process
and buffer incoming control packets in memory before propagating them. Because both IP cores generate
a new updated control packet before outputting an image data packet, this difference must be of little
consequence as the last control packet always takes precedence
Note: Altera recommends that you keep the default values for Number of packets buffered per frame
and Maximum packet length parameters, unless you intend to extend the Avalon-ST Video
protocol with custom packets.
UG-VIPSUITE
2015.05.04
Buffering of Non-Image Data Packets in Memory 2-29
Interfaces Altera Corporation
Send Feedback