C. additional information, Document revision history, Additional information – Altera Video and Image Processing Suite User Manual
Page 306
Additional Information
C
2015.05.04
UG-VIPSUITE
Additional information about the document and Altera.
Document Revision History
Date
Version
Changes
May 2015
2015.05.04 • Edited the description of the
Input (0-3) Enable
registers for the
Mixer II IP core. The 1-bit registers are changed to 2-bit registers:
• Set to bit 0 of the registers to display input 0.
• Set to bit 1 of the registers to enable consume mode.
• Edited the description of the
Interrupt
register to unused for the
Color Space Converter II, Frame Buffer II (writer), and Test Pattern
Generator II IP cores.
• Edited the register information for the Switch II IP core:
• Changed the description of the
Interrupt
register to state that bit
0 is the interrupt status bit.
• Updated the description of the
Control
register to add that bit 1
of the register is the interrupt enable bit.
• Edited the typo in address 15 of the Switch II IP core— Dout12
Output Control changed to Dout11 Output Control.
• Edited the typos in the descriptions for
Output Width
and
Output
Height
registers for the Test Pattern Generator IP cores.
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