Altera Video and Image Processing Suite - Manual (Page 167)

If the external memory in your system runs at a different clock rate to the Deinterlacing IP cores, you can
turn on an option to use a separate clock for the Avalon-MM master interfaces and use the memory clock
to drive these interfaces. To prevent memory read and write bursts from being spread across two adjacent
memory rows, you can turn on an option to align the initial address of each read and write burst to a
multiple of the burst target used for the read and write masters (or the maximum of the read and write
burst targets if using different values).
Note: Turning on this option may have a negative impact on memory usage but increases memory
efficiency.
Frame Rate Conversion
When you select triple-buffering, the decision to drop and repeat frames is based on the status of the spare
buffer. Because the input and output sides are not tightly synchronized, the behavior of the Deinterlacer is
not completely deterministic and can be affected by the burstiness of the data in the video system. This
may cause undesirable glitches or jerky motion in the video output.
By using a double-buffer and controlling the dropping/repeating behavior, the input and output can be
kept synchronized. For example, if the input has 60 interlaced fields per second, but the output requires
50 progressive frames per second (fps), setting the input frame rate to 30 fps and the output frame rate at
50 fps guarantees that exactly one frame in six is dropped.
To control the dropping/repeating behavior and to synchronize the input and output sides, you must
select double-buffering mode and turn on Run-time control for locked frame rate conversion in the
Parameter Settings tab of the parameter editor. The input and output rates can be selected and changed at
run time. Table 15–5 on page 15–15 lists the control register map.
The rate conversion algorithm is fully compatible with a progressive input stream when the progressive
passthrough mode is enabled but it cannot be enabled simultaneously with the run-time override of the
motion-adaptive algorithm.
Note: Only Deinterlacer IP core supports triple-buffering.
Bandwidth Requirement Calculations for 10-bit YCbCr Video
Because the memory subsystem packs 20-bit colors in 256-bit data words, some of the bits in a data word
are unused. These bits must be factored into the bandwidth requirement calculations.
The bandwidth calculation slightly differs for the Deinterlacer II and Broadcast Deinterlacer IP cores.
12-8 Frame Rate Conversion
UG-VIPSUITE
2015.05.04
Altera Corporation Deinterlacing IP Cores
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