Altera Video and Image Processing Suite User Manual
Page 212
Table 14-10: Frame Buffer II Control Register Map for the Writer
The table below describes the control register map for the writer component.
Note: Addresses 4, 5, and 6 are optional and only visible on the control interface when you turn on Locked rate
support in the parameter editor.
Address
Register
Description
0
Control
Bit 0 of this register is the
Go
bit, all other bits are unused.
Setting this bit to 0 causes the IP core to stop the next time
control information is read.
1
Status
Bit 0 of this register is the
Status
bit, all other bits are unused.
2
Interrupt
Unused.
3
Frame Counter
Read-only register updated at the end of each frame processed
by the writer. The counter is incremented if the frame is not
dropped and passed to the reader.
4
Drop Counter
Read-only register updated at the end of each frame processed
by the writer. The counter is incremented if the frame is
dropped.
5
Controlled Rate
Conversion
Bit 0 of this register determines whether dropping and
repeating of frames or fields is tightly controlled by the
specified input and output frame rates. Setting this bit to 0
switches off the controlled rate conversion, and returns the
triple-buffering algorithm to a free regime where dropping
and repeating is only determined by the status of the spare
buffer.
6
Input Frame Rate
Write-only register. A 16-bit integer value for the input frame
rate. This register cannot be read.
7
Output Frame Rate
Write-only register. A 16-bit integer value for the output
frame rate. This register cannot be read.
Table 14-11: Frame Buffer II Control Register Map for the Reader
The table below describes the control register map for the reader component.
Address
Register
Description
0
Control
Bit 0 of this register is the
Go
bit, all other bits are unused.
Setting this bit to 0 causes the IP core to stop the next time
control information is updated. While stopped, the IP core
may continue to receive and drop frame at its input if you
enable frame dropping.
1
Status
Bit 0 of this register is the
Status
bit, all other bits are unused.
UG-VIPSUITE
2015.05.04
Frame Buffer Control Registers
14-15
Frame Buffer IP Cores
Altera Corporation