Altera Video and Image Processing Suite - Manual (Page 157)

Control Synchronizer Signals
Table 11-2: Control Synchronizer Signals
Signal Direction Description
clock
Input The main system clock. The IP core operates on the rising
edge of this signal.
reset
Input The IP core asynchronously resets when this signal is high.
You must deassert this signal synchronously to the rising
edge of the clock signal.
din_data
Input
din
port Avalon-ST
data
bus. This bus enables the
transfer of pixel data into the IP core.
din_endofpacket
Input
din
port Avalon-ST
endofpacket
signal. This signal
marks the end of an Avalon-ST packet.
din_ready
Output
din
port Avalon-ST
ready
signal. This signal indicates
when the IP core is ready to receive data.
din_startofpacket
Input
din
port Avalon-ST
startofpacket
signal. This signal
marks the start of an Avalon-ST packet.
din_valid
Input
din
port Avalon-ST
valid
signal. This signal identifies the
cycles when the port must enter data.
dout_data
Output
dout
port Avalon-ST
data
bus. This bus enables the
transfer of pixel data out of the IP core.
dout_endofpacket
Output
dout
port Avalon-ST
endofpacket
signal. This signal
marks the end of an Avalon-ST packet.
dout_ready
Input
dout
port Avalon-ST
ready
signal. The downstream
device asserts this signal when it is able to receive data.
dout_startofpacket
Output
dout
port Avalon-ST
startofpacket
signal. This signal
marks the start of an Avalon-ST packet.
dout_valid
Output
dout
port Avalon-ST
valid
signal. The IP core asserts this
signal when it produces data.
slave_av_address
Input slave port Avalon-MM
address
bus. This bus specifies a
word offset into the slave address space.
slave_av_read
Output slave port Avalon-MM
read
signal. When you assert this
signal, the slave port sends new data at
readdata
.
slave_av_readdata
Output slave port Avalon-MM
readdata
bus. The IP core uses
these output lines for read transfers.
slave_av_write
Input slave port Avalon-MM
write
signal. When you assert this
signal, the
gamma_lut
port accepts new data from the
writedata
bus.
UG-VIPSUITE
2015.05.04
Control Synchronizer Signals 11-5
Control Synchronizer IP Core Altera Corporation
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