Altera Video and Image Processing Suite - Manual (Page 18)

IP Core Configuration ALM RAM DSP
Scaler II
• Symbols in parallel = 3
• Scaling algorithm = Polyphase
• Enable run-time control of input/output
frame size = On
• Vertical/horizontal filter taps = 4
• Vertical/horizontal filter phases = 14
1,010 12 12
Test Pattern
Generator
• Color space = RGB
• Run-time control of image size = Off
65 0 0
Trace System
• Buffer size = 8192
• Bit width of capture interface(s) = 32
• Number of inputs = 2
1,224 12 0
Stall Behavior and Error Recovery
The Video and Image Processing Suite IP cores do not continuously process data. Instead, they use flow-
controlled Avalon-ST interfaces, which allow them to stall the data while they perform internal
calculations.
During control packet processing, the IP cores might stall frequently and read or write less than once per
clock cycle. During data processing, the IP cores generally process one input or output per clock cycle.
There are, however, some stalling cycles. Typically, these are for internal calculations between rows of
image data and between frames/fields.
When stalled, an IP core indicates that it is not ready to receive or produce data. The time spent in the
stalled state varies between IP cores and their parameterizations. In general, it is a few cycles between rows
and a few more between frames.
If data is not available at the input when required, all of the IP cores stall and do not output data. With the
exceptions of the Deinterlacer and Frame Buffer in double or triple-buffering mode, none of the IP cores
overlap the processing of consecutive frames. The first sample of frame
F
+ 1 is not input until after the IP
cores produce the last sample of frame
F
.
When the IP cores receive an
endofpacket
signal unexpectedly (early or late), the IP cores recover from
the error and prepare for the next valid packet (control or data).
1-12 Stall Behavior and Error Recovery
UG-VIPSUITE
2015.05.04
Altera Corporation Video and Image Processing Suite Overview
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