Device family support, Device family support -4 – Altera Video and Image Processing Suite User Manual
Page 10
Device Family Support
The table below lists the device support information for the Video and Image Processing Suite IP cores.
Table 1-3: Device Family Support
Device Family
Support
Arria II GX / Arria II GZ
Final
Arria V
Final
Arria 10
Final—Supports only the following IP cores:
• Avalon-ST Video Monitor
• Broadcast Deinterlacer
• Clipper II
• Clocked Video Input
• Clocked Video Input II
• Clocked Video Output
• Clocked Video Output II
• Color Space Converter II
• Deinterlacer II
• Frame Buffer II
• Mixer II
• Scaler II
• Switch II
• Test Pattern Generator II
Cyclone IV ES / Cyclone IV GX
Final
Cyclone V
Final
MAX 10
Final
Stratix IV
Final
Stratix V
Final
Other device families
No support
Related Information
Provides more information about the support levels and current status.
1-4
Device Family Support
UG-VIPSUITE
2015.05.04
Altera Corporation
Video and Image Processing Suite Overview
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)