Altera Video and Image Processing Suite - Manual (Page 34)

Figure 2-6: Separate Synchronization Signals Timing Diagram
vid_de/vid_datavalid (1)
D0 DN vid_data
(1): vid_datavalid: Clocked Video Output IP core
vid_de: Clocked Video Input IP core
D1 Dn+2 Dn+1
vid_v_sync
vid_h_sync
vid_f
The CVI IP cores only read the
vid_data
,
vid_de
,
vid_h_sync
,
vid_v_sync
, and
vid_f
signals when
vid_datavalid
is 1. This allows the CVI IP cores to support oversampling where the video clock is
running at a higher rate than the pixel clock.
Video Locked Signal
The
vid_locked
signal indicates that the clocked video stream is active. When the signal has a value of 1,
the CVI IP cores take the input clocked video signals as valid, and read and process them as normal.
When the signal has a value of 0 (if for example the video cable is disconnected or the video interface is
not receiving a signal):
• Clocked Video Input IP core: The IP core takes the input clocked video signals as invalid and do not
process them.
• Clocked Video Input II IP core: The
vid_clk
domain registers of the IP core are held in reset and no
video is processed. The control and Avalon-ST Video interfaces are not held in reset and will respond
as normal. The
vid_locked
signal is synchronized internally to the IP core and is asynchronous to the
vid_clk
.
If the
vid_locked
signal goes invalid while a frame of video is being processed, the CVI IP cores end the
frame of video early.
Avalon-ST Video Protocol
The Avalon-ST Video protocol is a packet-oriented way to send video and control data over Avalon-ST
connections. The IP cores in the Video and Image Processing Suite use the Avalon-ST Video protocol.
Using the Avalon-ST Video protocol allows the construction of image processing data paths which
automatically configure to changes in the format of the video being processed. This minimizes the
external control logic required to configure a video system.
UG-VIPSUITE
2015.05.04
Avalon-ST Video Protocol 2-7
Interfaces Altera Corporation
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