Altera Video and Image Processing Suite User Manual
Page 225
Figure 17-1: Polyphase Mode Scaler Block Diagram
The figure below shows the flow of data through an instance of the Scaler II in polyphase mode.
∑
Cv 0
Bit Narrowing
Register Delay
∑
Bit Narrowing
Line Buffer
Delay
Line Buffer
Delay
Register Delay
Ch 0
Cv 1
Cv Nv
Ch 1
Ch Nh
Data from multiple lines of the input image are assembled into line buffers–one for each vertical tap.
These data are then fed into parallel multipliers, before summation and possible loss of precision. The
results are gathered into registers–one for each horizontal tap. These are again multiplied and summed
before precision loss down to the output data bit width.
Note: The progress of data through the taps (line buffer and register delays) and the coefficient values in
the multiplication are controlled by logic that is not present in the diagram.
Consider the following for an instance of the polyphase scaler.
17-4
Polyphase and Bicubic Algorithm
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2015.05.04
Altera Corporation
Scaler II IP Core
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
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- MAX 10 Clocking and PLL (86 pages)
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- MAX 10 FPGA (56 pages)
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- ALTDQ_DQS2 (100 pages)
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- Cyclone V Avalon-ST (248 pages)
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- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
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- Avalon Verification IP Suite (224 pages)
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- FFT MegaCore Function (50 pages)
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- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
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- Parallel Flash Loader IP (57 pages)
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