Altera Video and Image Processing Suite User Manual
Page 8
IP Core
Feature Support
Pixels in Parallel
4:2:2 Support
Interlaced
Clocked Video
Output (CVO)
No
Yes
Yes
Clocked Video
Output II (CVO II)
Yes
Yes
Yes
Color Plane
Sequencer
No
Yes
Yes
Color Space
Converter (CSC)
No
No
Yes
Color Space
Converter II (CSC
II)
Yes
No
Yes
Control Synchron‐
izer
No
Yes
Yes
Deinterlacer
No
Yes
Yes
Deinterlacer II
No
Yes
Yes
Broadcast Deinter‐
lacer
No
Yes
Yes
Frame Buffer
No
Yes
Yes
Frame Buffer II
Yes
Yes
Yes
Frame Reader
No
Yes
Yes
Gamma Corrector
No
Yes
Yes
Interlacer
No
Yes
Yes
(3)
Mixer II
Yes
Yes
Yes
(1)
Scaler II
No
Yes
Yes
(2)
Switch
No
Yes
Yes
Switch II
Yes
Yes
Yes
Test Pattern
Generator
No
Yes
Yes
(4)
Test Pattern
Generator II
Yes
Yes
Yes
(4)
(3)
The IP core either discards or propagates without change the interlaced data if you select Pass-through
mode in the parameter editor.
(4)
For interlaced data NTSC, mismatched line counts of F0 and F1 are not supported.
1-2
Video and Image Processing Suite Overview
UG-VIPSUITE
2015.05.04
Altera Corporation
Video and Image Processing Suite Overview
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)