Altera Video and Image Processing Suite User Manual
Page 251
Address
Register
Description
4
R/Y
The value of the R (or Y) color sample when the test pattern is
a uniform color background.
Note: Available only when the IP core is configured to
produce a uniform color background and run-time
control interface is enabled.
5
G/Cb
The value of the G (or Cb) color sample when the test pattern
is a uniform color background.
Note: Available only when the IP core is configured to
produce a uniform color background and run-time
control interface is enabled.
6
B/Cr
The value of the B (or Cr) color sample when the test pattern
is a uniform color background.
Note: Available only when the IP core is configured to
produce a uniform color background and run-time
control interface is enabled.
Table 19-7: Test Pattern Generator II Control Register Map
The table below describes the control register map for Test Pattern Generator II IP core.
Address
Register
Description
0
Control
Bit 0 of this register is the
Go
bit, all other bits are unused.
Setting this bit to 0 causes the IP core to stop before control
information is read.
1
Status
Bit 0 of this register is the
Status
bit, all other bits are unused.
The IP core sets this address to 0 between frames. The IP core
sets this address to 1 while it is producing data and cannot be
stopped.
2
Interrupt
Unused.
3
Output Width
The width of the output frames or fields in pixels.
Note: Value from 32 up to the maximum specified in the
parameter editor.
4
Output Height
The progressive height of the output frames or fields in pixels.
Note: Value from 32 up to the maximum specified in the
parameter editor.
UG-VIPSUITE
2015.05.04
Test Pattern Generator Control Registers
19-9
Test Pattern Generator IP Cores
Altera Corporation