Altera Video and Image Processing Suite - Manual (Page 195)

Signal Direction Description
dout_ready
Input
dout
port Avalon-ST
ready
signal. The downstream
device asserts this signal when it is able to receive data.
dout_startofpacket
Output
dout
port Avalon-ST
startofpacket
signal. This signal
marks the start of an Avalon-ST packet.
dout_valid
Output
dout
port Avalon-ST
valid
signal. The IP core asserts this
signal when it produces data.
slave_av_address
Input slave port Avalon-MM
address
bus. This bus specifies a
word offset into the slave address space.
slave_av_read
Input slave port Avalon-MM read signal. When you assert this
signal, the slave port drives new data onto the read data
bus.
slave_av_readdata
Output slave port Avalon-MM
readdata
bus. The IP core uses
these output lines for read transfers.
slave_av_write
Input slave port Avalon-MM
write
signal. When you assert this
signal, the
gamma_lut
port accepts new data from the
writedata
bus.
slave_av_writedata
Input slave port Avalon-MM
writedata
bus. The IP core uses
these input lines for write transfers.
slave_av_irq
Output slave port Avalon-MM
interrupt
signal. Asserted to
indicate that the interrupt registers of the IP core are
updated; and the master must read them to determine
what has occurred.
master_av_clock
Input master port
clock
signal. The interface operates on the
rising edge of the
clock
signal.
master_av_reset
Input master port reset signal. The interface asynchronously
resets when this signal is high. You must deassert this
signal synchronously to the rising edge of the clock signal.
master_av_address
Output master port Avalon-MM
address
bus. This bus specifies a
byte address in the Avalon-MM address space.
master_av_burstcount
Output master port Avalon-MM
burstcount
signal. This signal
specifies the number of transfers in each burst.
master_av_read
Output master port Avalon-MM
read
signal. The IP core asserts
this signal to indicate read requests from the master to the
system interconnect fabric.
master_av_readdata
Input master port Avalon-MM
readdata
bus. These input lines
carry data for read transfers.
master_av_readdatavalid
Input master port Avalon-MM
readdatavalid
signal. The
system interconnect fabric asserts this signal when the
requested read data has arrived.
13-4 Frame Reader Signals
UG-VIPSUITE
2015.05.04
Altera Corporation Frame Reader IP Core
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