Altera Video and Image Processing Suite - Manual (Page 74)

Table 4-8: AFD Inserter Register Map
Address Register Description
0 Control
• When bit 0 is 0, the core discards all packets.
• When bit 0 is 1, the core passes through all non-ancillary
packets.
1 — Reserved.
2 — Reserved.
3 AFD Bits 0-3 contain the active format description code.
4 AR Bit 0 contains the aspect ratio code.
5 Bar data flags Bits 0-3 contain the bar data flags to insert.
6 Bar data value 1 Bits 0-15 contain bar data value 1 to insert.
7 Bar data value 2 Bits 0-15 contain bar data value 2 to insert.
8 AFD valid
• When bit 0 is 0, an AFD packet is not present for each
image packet.
• When bit 0 is 1, an AFD packet is present for each image
packet.
Modules for Clocked Video Input II IP Core
The architecture for the Clocked Video Input II IP core differs from the existing Clocked Video Input IP
core.
UG-VIPSUITE
2015.05.04
Modules for Clocked Video Input II IP Core 4-15
Clocked Video Interface IP Cores Altera Corporation
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