Altera Video and Image Processing Suite User Manual
Page 301
Figure A-7: Supported FOURCC Codes and Data Format
The figure below shows an example of the data format required by the file I/O class for each of the
supported FOURCC codes.
V or B 10
Y or G 10
U or B 10
Y 410 / A 2R 10 G 10 B 10
Y 210
Byte 0
2
3
5
1
4
7 6
0
Byte 1
Byte 2
Byte 3
U
Y
Byte 0
Byte 1
Byte 2
Byte 3
U
Y
V
YUY 2
Y
IYU 2
Byte 4
Byte 5
Byte 6
Byte 7
V
Y
2
3
5
1
4
7 6
0
2
3
5
1
4
7 6
0
2
3
5
1
4
7 6
0
2
3
5
1
4
7 6
0
2
3
5
1
4
7 6
0
2
3
5
1
4
7 6
0
2
3
5
1
4
7 6
0
2
3
5
1
4
7 6
0
2
3
5
1
4
7 6
0
2
3
5
1
4
7 6
0
2
3
5
1
4
7 6
0
Byte 0
Byte 1
Byte 2
Byte 3
V
0
Y
0
U
0
U
1
2
3
5
1
4
7 6
0
2
3
5
1
4
7 6
0
2
3
5
1
4
7 6
0
2
3
5
1
4
7 6
0
Byte 4
Byte 5
Byte 6
Byte 7
U
2
V
1
Y
1
Y
2
2
3
5
1
4
7 6
0
2
3
5
1
4
7 6
0
2
3
5
1
4
7 6
0
2
3
5
1
4
7 6
0
Byte 0
Byte 1
Byte 2
Byte 3
G
B
RGB 32
R
2
3
5
1
4
7 6
0
2
3
5
1
4
7 6
0
2
3
5
1
4
7 6
0
2
3
5
1
4
7 6
0
Byte 0
Byte 1
Byte 2
Byte 3
2
3
5
1
4
7 6
0
2
3
5
1
4
7 6
0
2
3
5
1
4
7 6
0
2
3
5
1
4
7 6
0
UG-VIPSUITE
2015.05.04
Raw Video Data Format
A-33
Avalon-ST Video Verification IP Suite
Altera Corporation
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
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- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)