Altera Video and Image Processing Suite - Manual (Page 64)

Interrupts
The CVI IP cores produce a single interrupt line.
Table 4-5: Internal Interrupts
The table below lists the internal interrupts of the interrupt line.
IP Core Internal Interrupts Description
Clocked Video Input IP core
Status update interrupt Triggers when a change of resolution in the
incoming video is detected.
Stable video interrupt
• Triggers when the incoming video is
detected as stable (has a consistent sample
length in two of the last three lines) or
unstable (if, for example, the video cable is
removed).
• The incoming video is always detected as
unstable when the
vid_locked
signal is
low.
Clocked Video Input II IP core
Status update interrupt Triggers when the stable bit, the vid locked
bit or the resolution valid bit of the
Status
register changes value.
End of field/frame
interrupt
• If the synchronization settings are set to
Any field first, triggers on the falling edge
of the v sync.
• If the synchronization settings are set to
F1 first, triggers on the falling edge of the
F1 v sync.
• If the synchronization settings are set to
F0 first, you can use the interrupt to
trigger the reading of the ancillary packets
from the control interface before they are
overwritten by the next frame.
These interrupts can be independently enabled using bits [2:1] of the
Control
register. Their values can be
read using bits [2:1] of the
Interrupt
register. Writing 1 to either of these bits clears the respective
interrupt.
Clocked Video Output Video Modes
The video frame is described using the mode registers that are accessed through the Avalon-MM control
port.
If you turn off Use control port in the parameter editor for the CVO IP cores, then the output video
format always has the format specified in the parameter editor.
UG-VIPSUITE
2015.05.04
Interrupts 4-5
Clocked Video Interface IP Cores Altera Corporation
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