Altera Video and Image Processing Suite - Manual (Page 27)

IP Core Stall Behavior Error Recovery
Enabling run-time control of resolutions
affects stalling between frames:
• With no run-time control: about 10
cycles of delay before the stall behavior
begins, and about 20 cycles of further
stalling between each output line.
• With run-time control of resolutions:
about additional 25 cycles of delay
between frames.
Switch/
Switch II
• Only stalls its inputs when performing
an output switch.
• Before switching its outputs, the IP core
synchronizes all its inputs and the inputs
may be stalled during this synchroniza‐
tion.
—
Test Pattern
Generator/
Test Pattern
Generator II
• All modes stall for a few cycles after a
field control packet, and between lines.
• When producing a line of image data,
the IP core produces one sample output
on every clock cycle, but it can be stalled
without consequences if other functions
down the data path are not ready and
exert backpressure.
—
UG-VIPSUITE
2015.05.04
Stall Behavior and Error Recovery 1-21
Video and Image Processing Suite Overview Altera Corporation
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